/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* GICC registers */
- mov_imm x17, GXBB_GICC_BASE
+ mov_imm x17, AML_GICC_BASE
adr x6, gicc_regs
ldr w8, [x17, #GICC_HPPIR]
/* GICD registers */
- mov_imm x16, GXBB_GICD_BASE
+ mov_imm x16, AML_GICD_BASE
add x7, x16, #GICD_ISPENDR
adr x4, gicd_pend_reg
};
static const gicv2_driver_data_t gxbb_gic_data = {
- .gicd_base = GXBB_GICD_BASE,
- .gicc_base = GXBB_GICC_BASE,
+ .gicd_base = AML_GICD_BASE,
+ .gicc_base = AML_GICC_BASE,
.interrupt_props = gxbb_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props),
};
/*******************************************************************************
* GIC-400 and interrupt handling related constants
******************************************************************************/
-#define GXBB_GICD_BASE UL(0xC4301000)
-#define GXBB_GICC_BASE UL(0xC4302000)
+#define AML_GICD_BASE UL(0xC4301000)
+#define AML_GICC_BASE UL(0xC4302000)
#define IRQ_SEC_PHY_TIMER 29
};
static const gicv2_driver_data_t gxbb_gic_data = {
- .gicd_base = GXBB_GICD_BASE,
- .gicc_base = GXBB_GICC_BASE,
+ .gicd_base = AML_GICD_BASE,
+ .gicc_base = AML_GICC_BASE,
.interrupt_props = gxbb_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props),
};
/*******************************************************************************
* GIC-400 and interrupt handling related constants
******************************************************************************/
-#define GXBB_GICD_BASE UL(0xC4301000)
-#define GXBB_GICC_BASE UL(0xC4302000)
+#define AML_GICD_BASE UL(0xC4301000)
+#define AML_GICC_BASE UL(0xC4302000)
#define IRQ_SEC_PHY_TIMER 29